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Update: An Intel spokesperson has provided TR with a brief statement on the TSX erratum, confirming that Intel has "addressed the issue" and "disabled the TSX feature on affected products." He further stated that Intel is "committed to the feature" over the long run and plans to "re implement it in future processors." We have inquired about how the TSX erratum will affect upcoming Haswell EP series server CPUs and will post another update if we learn more.
The launch of Intel high volume Haswell EP processors is rapidly approaching, and the TSX errata apparently won delay that product launch. Instead, a spokesperson for the firm informs us that TSX will be available for software developers to enable "for development purposes" on Haswell EP, so that their code will be "ready for production" once the higher end Haswell EX processors arrive at a later date.
Intel has a fix in the works for Broadwell next stepping. We don yet know when Broadwell production will transition to the new stepping or how prevalent the TSX erratum will be among the first wave of Broadwell based systems.
As is customary in such cases, Intel has disabled the TSX instructions in current products using a CPU microcode update delivered via new revisions of motherboard firmware. Disabling TSX should ensure stable operation for Haswell CPUs, but those chips will no longer be capable of supporting TSX features, including hardware lock elision and restricted transactional memory.
I believe my friend David Kanter was first to report this problem via a tweet the other day. Intel revealed the news of the erratum to a group of journalists during briefings in Portland last week. I was among those in attendance and was able to talk with Intel architects about the situation.
Also, because the problem is apparently restricted to the use of TSX instructions, this erratum isn likely to prompt the sort of dire consequences the TLB erratum in AMD Barcelona chip did. As we exclusively reported at the time, the Barcelona TLB problem caused AMD to stop the shipment of Opteron Air Max 2016 White Womens processors and issue a performance impacting microcode patch for consumer Phenom CPUs. By contrast, the most unfortunate impact of this TSX erratum may be to slow the development of TSX capable software.
In other words, we expect Haswell EP to ship on schedule with Nike Air Max White Red Black
The TSX instructions built into Intel Haswell CPU cores haven become widely used by everyday software just yet, but they promise to make certain types of multithreaded applications run much faster than they can today. Some of the savviest software developers are likely building TSX enabled software right about now.
This erratum was evidently discovered quite recently, too late for a fix to be included in the first revision of Intel upcoming Broadwell Y series chips. As we reported yesterday, Intel is currently shipping production Broadwell Y silicon to its customers for use in Core M based tablets this holiday season. These first production Broadwell chips will also have TSX disabled via microcode.
the TSX erratum still etched into its silicon and TSX instructions disabled via a microcode patch. Those who wish to risk working with TSX in Haswell EP will have the option to enable it via a firmware menu, but Intel recommends waiting for Haswell EX before using TSX in production systems.
Given that most Haswell and all Broadwell CPUs affected Nike Air Max Ultra Bw
Intel will surely issue new steppings of its production Haswell processors with the TSX erratum fully corrected in hardware, but the firm hasn stated any timetables for the delivery of revised chips.
Unfortunately, that work may have to come to a halt, thanks to a bug "errata," as Intel prefers to call them Haswell TSX implementation that can cause critical software failures.
are shipping in consumer class systems, the impact of this TSX snafu ought to be relatively minimal. The obvious initial targets for TSX optimization are server class applications like transactional database servers. At present, Intel server class Xeon lineup relies on the older Ivy Bridge core, which lacks TSX entirely.
The TSX problem was apparently discovered by a software developer outside of Intel, and the company then confirmed the erratum through its own testing. Errata of this magnitude aren often discovered this late in the life of a CPU core.
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Update II: Intel has gotten back to us with some more information about how the TSX erratum affects its upcoming Xeon CPUs.
single socket, enthusiast oriented Haswell E processors are based on the same silicon as the lower end Xeon EP parts, I expect the upcoming Core i7 Extreme CPUs to have TSX disabled in microcode, as well.
Errata prompts Intel to disable TSX in Haswell
Software developers who wish to continue working with TSX will have to avoid updating their systems to newer firmware revisions in doing so, they retain the risk of TSX related memory corruption or crashes.
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